(a) Field of the Invention
The present invention relates to a plasma display panel (PDP) driving circuit. More specifically, the present invention relates to an address driving circuit for applying address voltages.
(b) Description of the Related Art
The PDP is a flat display that uses plasma generated via a gas discharge process to display characters or images, and, depending on its size, tens to millions of pixels are provided thereon in a matrix format PDPs are categorized as direct current (DC) PDPs or alternating current (AC) PDPs according to the supplied driving voltage waveforms and discharge cell structures.
DC PDPs have electrodes exposed in the discharge space. As a result, they allow current to flow in the discharge space while voltage is supplied and therefore require resistors for current restriction. AC PDPs, on the other hand, have electrodes covered by a dielectric layer, due to which capacitances are naturally formed to restrict the current, and the electrodes are protected from ion shocks during discharge. As a result, AC PDPs have a longer lifespan than DC PDPs.
FIG. 1 shows a perspective view of an AC PDP;
As shown, a scan electrode 4 and a sustain electrode 5, disposed over a dielectric layer 2 and a protection film 3, are provided in parallel and form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 are installed on a second glass substrate 6. Barrier ribs 9 are formed in parallel with the address electrodes 8, on the insulation layer 7 between the address electrodes 8, and phosphor 10 is formed on the surface of the insulation layer 7 between the barrier ribs 9. The first and second glass substrates 1 and 6 having a discharge space 11 between them are provided facing each other so that the scan electrode 4 and the sustain electrode 5 may respectively cross an address electrode 8. An address electrode 8 and a discharge space 11 formed at a crossing part of the scan electrode 4 and the sustain electrode 5 form a discharge cell 12.
FIG. 2 shows a PDP electrode arrangement diagram.
As shown, the PDP electrode has an m×n matrix configuration, and in detail, it has address electrodes A1 to Am in the column direction, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn in the row direction, alternately. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
In general, a method for driving the AC PDP includes a reset period, an address period, a sustain period, and an erase period.
In the reset period, the states of the respective cells are reset to address the cells smoothly. In the addressing period, the cells in a panel to be turned on and the cells not to be turned on are selected, and wall charges are accumulated in the cells to be turned on (i.e., the addressed cells). In the sustain period, discharge is performed to actually display pictures on the addressed cells. In the erase period, the wall charges of the cells are reduced to terminate the sustain.
Because a discharge space between a scan electrode and a sustain electrode and a discharge space between a surface on which an address electrode is formed and a surface on which scan and sustain electrodes are formed operate as capacitive loads (referred to as panel capacitors hereinafter), capacitance exists on the panel. Hence, in addition to power for addressing, reactive power is also needed to apply waveforms for addressing. Therefore, a PDP address driving circuit includes a power recovery circuit for recovering the reactive power and re-using the same, as disclosed by the power recovery circuit of L. F. Weber in U.S. Pat. Nos. 4,866,349 and 5,081,400.
Conventional power recovery circuits fail to recover 100% of the reactive power during the power recovery process due to switching losses in the transistors or parasitic components of the circuit. As a result, the power recovery operation cannot set the voltage at the panel capacitor to a desired voltage, and the switch must perform hard switching.
When all the discharge cells are turned on in a specific subfield, it is necessary for addressing to apply a voltage to the address electrode. The conventional power recovery circuit continues to perform power recovery in this case, even though power recovery is not necessary, thereby worsening efficiency.